This invention relates to antenna beamformers for shaping antenna beams, and more particularly to such antenna beam formers capable of providing sidelobe or mainbeam cancellation.
Many modern communication and sensing systems include a plurality of antennas arranged as an array or as a main antenna with auxiliary antennas, arranged for producing a mainbeam with reduced amplitude or suppressed sidelobes, or in some cases with a suppressed mainlobe or portion thereof. For example, a radar system may include a main antenna for forming a narrow beam, which is subject to unwanted signals from the main antenna sidelobes. Auxiliary antennas located near the main antenna may be interconnected therewith for reducing the amount of effective signal intrusion on the sidelobes.
FIG. 1a is a simplified block diagram of a signal receiving system designated generally as 10 which includes a main antenna 12 and a plurality of auxiliary antennas 14a, 14b, . . . 14n. Main antenna 12 is connected by way of a diplexer 16 to a transmitter (TX) 18 and to a receiver (RX) 20. Transmitter signals are coupled to antenna 12 by diplexer 16, and received signals are coupled by diplexer 16 to receiver 20. Receiver 20 may perform a number of functions, including bandpass filtering for rejection of unwanted signals lying outside the desired bandpass, and down conversion to an intermediate frequency (IF). The main IF signal is coupled over a path 22 to an analog-to-digital converter (ADC) 24. ADC 24 produces digital signals which are applied over a data path 26 to a digital product detector (DPD) 28. DPD 28, described in more detail below, converts the in-phase (I) and quadrature (Q) components of the main IF signal to baseband or to zero frequency.
Auxiliary antennas 14a, 14b, . . . 14n are not coupled to transmitters, and therefore function only in a receiving mode. Each of antennas 14a, 14b, . . . 14n is connected to its own receiver, analog-to-digital converter, and digital product detector, so only one such cascade is described. Taking auxiliary antenna 14a as representative, the signals which it receives are coupled over a path 30a to a receiver 32a, which performs the same functions as receiver 20, including bandpass filtering and down conversion to IF on a transmission path 34a. The auxiliary received signal on transmission path 34a is sampled and digitized in ADC 36a to produce sampled, digitized IF signals on data path 38a for application to digital product detector (DPD) 40a. DPD 40a detects the digitized IF signal on data path 38a to produce in-phase signal components on data path 42a1 and quadrature signal components on data path 42a2. Digital product detectors are known, and are described, for example, in U.S. Pat. No. 4,779,054 issued Oct. 18, 1988 in the name of Monteleone et al.
As so far described, the arrangement of FIG. 1a processes the main signal and the auxiliary signals to produce baseband in-phase and quadrature digital signals on data paths 29a and 29b, and in-phase and quadrature sets of auxiliary signals on data path pairs 42a, 42b, . . . 42n. The beamforming is accomplished by weighting the in-phase and quadrature components of the main signal on data paths 29a and 29b by the real and imaginary components of a weighting coefficient W.sub.0, and by similarly weighting each of the in-phase and quadrature components of the auxiliary baseband signals by the real and imaginary components of a set of weights W.sub.1, W.sub.2, . . . W.sub.n, as described in more detail below. The weighted main baseband signals generated in complex multiplier 44 are applied by way of data paths 48a and 48b to a complex adder 52. The weighted in-phase and quadrature components produced by each of multipliers 46a, 46b, . . . 46n on data path pairs 50a, 50b, . . . 50n, respectively, are applied to complex adding circuits 54a, 54b, . . . 54.sub.n-1. There is one less adder 54 than there are multipliers 46 because adder 54.sub.n-1 adds together the outputs from penultimate multiplier 46.sub.n-1 with the output from last multiplier 46n. Complex adder 54a adds together the weighted in-phase and quadrature baseband components from multiplier 46a together with the corresponding components from all of the other multipliers as added together by the remaining complex adders 54b, . . . 54.sub.n-1. The in-phase and quadrature components of the weighted baseband auxiliary signals at the output of complex summing circuit 54a are applied as one set of inputs to complex summing circuit 52. Complex summing circuit 52 sums the in-phase and quadrature components of the weighted baseband main signals with the in-phase and quadrature components, respectively, of the weighted baseband auxiliary signals to produce the desired in-phase and quadrature output signals on data paths 58a and 58b. The signals appearing on data paths 58a and 58b represent the signals received by main antenna 12 and auxiliary antennas 14 with nulling or signal suppression in directions controlled by the selection of weights W.sub.0, W.sub.1, . . . W.sub.n.
FIG. 1b is a simplified block diagram of a digital product detector (DPD) of FIG. 1a. For definiteness, FIG. 1b represents DPD 28 of FIG. 1a. In FIG. 1b, elements corresponding to those of FIG. 1 are designated by like reference numerals. In FIG. 1b, digitized intermediate-frequency main signals are applied over data path 26 to the common element 60a of a single pole, double throw switch 60. Switch 60 alternates position between terminals 61a and 61b during each clock pulse representing a new signal sample. Thus, a first sample may be applied by switch 60 in the illustrated position to switch terminal 61a, and the next following signal sample is applied to switch terminal 61b. The samples are continuously alternated between terminals 61a and 61b. FIG. 1c illustrates one cycle of intermediate-frequency analog equivalent of the input signal applied to switch 60 of FIG. 1b. In FIG. 1c, digital samples occur at times T0, T1, T2 and T3 for the case in which the sampling clock signal has a frequency of four times the intermediate frequency. Amplitudes a.sub.0, a.sub.1, a.sub.2 and a.sub.3 represent the amplitudes of the digital samples which might occur. When applied to alternating switch 60 of FIG. 1b, sample a.sub.0 might be applied to switch terminal 61.sub.a, in which case sample a.sub.1 would be applied to switch terminal 61b, a.sub.2 would be applied to switch terminal 61a, and sample a.sub.3 would be applied to switch terminal 61b. Thus, samples a.sub.0 and a.sub.2 are applied to a data path designated generally as 62a in FIG. 1b, while samples a.sub.1 and a.sub.3 are applied to a channel designated 62b. Channel 62b is identical to channel 62a, so only channel 62a is described in detail.
Samples a.sub.0 and a.sub.2 of FIG. 1c are applied by way of switch 60 of FIG. 1b to a mixer or multiplier 64a, to which a path-frequency clock signal designated (-1) to the n.sup.th power is applied, which simply represents multiplication of the sequential signal samples alternately by +1 and -1, thereby effecting a reversal of amplitude of every other sample. The structure of multiplier 64a is simpler than the structure of a general multiplier, since it is only required to negate or not negate. For example, sample a.sub.0 would be multiplied by +1 and negative-amplitude sample a.sub.2 would be multiplied by -1, to invert it and thereby produce a signal of unidirectional polarity. Thus, multiplier 64a "detects" the signal to produce a sample representation of a direct voltage, which is applied to a finite impulse response (FIR) filter 66a.
The purpose of FIR filter 66a and 66b can be explained by noting that the sampling of waveform 98 of FIG. 1c occurs at different times for the in-phase and quadrature components. Thus, the amplitudes of the in-phase and quadrature may not be true representations of the relative amplitudes which they would have if they were sampled at the same instant. FIR filters 66a and 66b perform interpolation to effectively "move" the sampling times into congruence, as known in the art. FIR filter 66a includes a delay line which, as illustrated, includes four shift registers (S) 68a, 68b, 68c and 68d, which together provide five sample points 70a, 70b, . . . 70e. Each tap 70a, 70b, . . . 70e is coupled to an input of a multiplier 72a, 72b, . . . 72e. A plurality of fixed or variable weighting signals are applied over a data path 74 to the multipliers 72, for multiplying the mutually delayed signal samples. The interpolation weights W.sub.I may be produced by a ROM, or calculated by an adaptive scheme. The mutually delayed signals, multiplied by interpolation weights, are applied to a summing circuit illustrated as 76, which produces the desired detected in-phase signal on data path 29a. Similarly, channel 62b of FIG. 1b produces on output data path 29b the desired quadrature baseband signal, by use of a different set of FIR weights W.sub.Q.
FIG. 1d is a simplified block diagram of a complex multiplier 44 or 46 of FIG. 1a. For definiteness, the arrangement of FIG. 1d represents complex multiplier 46a of FIG. 1a. Elements of FIG. 1d corresponding to those of FIG. 1a are designated by like reference numerals. In FIG. 1d, complex multiplier 46a includes four real multiplier 78a, 78b, 80a and 80b, and two real adders or summing circuits 82a and 82b. In-phase detected auxiliary signals are applied over data path 42a1 to first inputs of multiplier 78a and 80a, and quadrature detected auxiliary signals are applied over path 42a2 to first inputs of real multiplier 78b and 80b. Real components of weighting signal W.sub.1 are applied by way of data path 84a to second inputs of multipliers 78a and 78b, while imaginary components of weighting signal W.sub.1 are applied by way of data path 84b to second inputs of multipliers 80a and 80b. The weighted signals at the outputs of multipliers 78a and 80b are applied to inputs of a real adder 82a, configured for subtraction of the output of multiplier 80b from the output of multiplier 78a to produce the real component of weighted signal on output data path 50a1, and the outputs of multipliers 78b and 80a are applied to inputs of summing circuit 82b to produce the weighted imaginary signal on data path 50a2.
FIG. 1e is a simplified block diagram of a complex adder 52 or 54 of FIG. 1a. For definiteness, complex adder 54a is illustrated. In FIG. 1e, elements corresponding to those of FIG. 1a are designated by like reference numerals. In FIG. 1e, complex adder 54a includes first and second real adders 86a and 86b. In FIG. 1e, adder 86a sums together the real components of the weighted detected auxiliary signals received over data path 50a1 with the sum of the weighted detected auxiliary signals received over data path 56b1 to produce the sum of all the weighted detected auxiliary signals on data path 56a1. Similarly, adder 86b sums together the imaginary component of the detected auxiliary signal on data path 50a2 with the sum of the imaginary components of the weighted auxiliary signals received over 56b2 to produce the total sum of the imaginary components of the detected auxiliary signals on data path 56a2.
The arrangement of FIG. 1a requires a digital product detector 28 for the main signal path and a plurality of further digital product detectors 40a, 40b, . . . 40n, one for each of the auxiliary data paths. In addition, the arrangement of FIG. 1a requires a complex multiplier 44 or 46a, 46b, . . . 46n for each of the main and auxiliary data paths. By reference to FIGS. 1b, 1d and 1e, it is easy to see that each of the structures includes a number of real multipliers and summers, and that the overall structure may be quite complex. It would be desirable to reduce the total amount of hardware required to produce the sidelobe-cancelled output signals on data paths 58a and 58b.